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# Designing a Retro CPU from First Principles

I’ve been reading about retro computers recently and began wondering how feasible it would be to design and build one from scratch. To explore this idea, I decided to simulate a computer using one of the many online logic simulation tools available.

My tool of choice is **CircuitVerse**. It provides a clean, functional interface along with a number of sophisticated features that make it well suited to this kind of experimentation.

To guide the project, I’ve set myself a small number of rules.

---

## Design Rules

**Rule 1:**  
Everything must initially be built from a universal logic gate — either **NOR** or **NAND**.

**Rule 2:**  
Once I have constructed a module, I will allow myself to use the equivalent built-in CircuitVerse module in other designs.  
For example, after building an AND gate from first principles, I may then use the CircuitVerse AND gate module elsewhere.

---

## Project Scope

While there are already several CPU designs available on CircuitVerse, my interest here is in **documenting the construction process**, starting from basic logic gates and progressing incrementally toward a working CPU.

I won’t go into extensive detail on the underlying theory. There are many excellent resources available online for readers who want a deeper theoretical background.

---

## Design Parameters

- The design will begin with a **NOR gate**. Most designs I’ve seen tend to use NAND gates, so I’ve chosen NOR simply to be different. In practice, this choice mainly affects the earliest stages.
- The CPU will be **4-bit** rather than 8-bit. An 8-bit design felt too complex to be practical for constructing every component by hand.
- What can ultimately be achieved with a 4-bit CPU remains to be seen.
- The final design aims to include:
  - An **Arithmetic Logic Unit (ALU)**
  - Separate **RAM** and **ROM**
  - **Memory registers**
  - **Control logic**

---

## Notation

The following conventions will be used when labelling designs:

- **I** — Single-bit inputs  
- **Q** — Outputs  
- **A, B** — 4-bit inputs  
- **D** — Data lines  
- **E** — Enable lines (to activate or deactivate modules)  
- **S** — Select lines  
- **CLK** — Clock signal  

Multiple signals are indicated using subscripts.

A prime (`'`) denotes logical NOT. For example, `Q'` means **NOT(Q)**.

---

## Fundamental Logic Gates

To begin, the following fundamental logic gates are required:

- AND  
- OR  
- NAND  
- NOT  
- XOR  
- XNOR  

The first gate I constructed was the **NOT gate**, as it is particularly useful when creating AND and OR gates. These, in turn, are used to build more complex gates such as NAND and NOR.

All fundamental gates can be seen in the interactive window below. You can modify the inputs and observe the resulting outputs.

---

## Multiple-Input Logic Gates

Several multiple-input gates are also required, such as a **4-input AND gate**. Although CircuitVerse provides built-in modules for these, they must first be constructed from simpler gates to comply with the design rules.

For example, chaining two 2-input AND gates makes it straightforward to build a 3-input AND gate. Below are the constructions for the multiple-input gates used in this project.

Once the 4-input AND gate was completed, the built-in CircuitVerse version was used to construct a 5-input AND gate, in accordance with Rule 2.

---

## Interactive Circuit

<iframe src="https://circuitverse.org/simulator/embed/4-bit-alu-7457aee0-7e4f-4eed-a64c-21187b472ffc?theme=&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true"
        style="border-width:; border-style: dashed; border-color:;"
        name="myiframe"
        id="projectPreview"
        scrolling="no"
        frameborder="1"
        marginheight="0px"
        marginwidth="0px"
        height="500"
        width="500"
        allowfullscreen>
</iframe>


this is second post

Cache Components are a new set of features designed to make caching in Next.js both more explicit, and more flexible. They center around the new 

 directive, which can be used to cache pages, components, and functions, and which leverages the compiler to automatically generate cache keys wherever it’s used. #new

Unlike the implicit caching found in previous versions of the App Router, caching with Cache Components is entirely opt-in. All dynamic code in any page, layout, or API route is executed at request time by default, giving Next.js an out-of-the-box experience that’s better aligned with what developers expect from a full-stack application framework.

Cache Components also complete the story of Partial Prerendering (PPR), which was first introduced in 2023. Prior to PPR, Next.js had to choose whether to render each URL statically or dynamically; there was no middle ground. PPR eliminated this dichotomy, and let developers opt portions of their static pages into dynamic rendering (via Suspense) without sacrificing the fast initial load of fully static pages.

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